1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a technique of forming a trench MOS gate which is applied to a power device.
2. Description of the Background Art
FIGS. 41 to 48 are sectional views showing a conventional process of forming trench MOS gates in step order. First, the structure shown in FIG. 41 is prepared. Referring to FIG. 41, the structure is obtained by successively stacking a P-type semiconductor layer 103 having a high impurity concentration, an N-type semiconductor layer 102 having a high impurity concentration, an N-type semiconductor layer 101 having a low impurity concentration and a P-type base layer 104 from the lower side, and trenches 200 are formed between an upper surface of the P-type base layer 104 and an intermediate portion of the N-type semiconductor layer 101. On the upper surface of the P-type base layer 104, N-type semiconductor layers 105 having a high impurity concentration are selectively formed around the trenches 200.
Then, a gate oxide film 111 is formed over the entire surface, including inner walls of the trenches 200, exposed on the upper side of the structure shown in FIG. 41 (FIG. 42). Further, a gate electrode material layer 112 of polysilicon or the like is provided on the gate oxide film 111, to fill up the trenches 200 (FIG. 43). Only the parts of the gate electrode material layer 112 filling up the trenches 200 are left as gate electrodes 113, and the remaining parts are removed by etching (FIG. 44).
Thereafter surfaces of the gate electrodes 113 are oxidized to form oxide films 115 (FIG. 45). P-type semiconductor layers 118 having a high impurity concentration are formed on parts of the P-type base layer 104 exposed between the adjacent N-type semiconductor layers 105 by ion implantation through the oxide films 111 or the like, and interlayer isolation films 116 and 117 are deposited in this order with oxide films formed by CVD, for example (FIG. 46). The interlayer isolation films 116 and 117 are selectively etched to be left only on the gate electrodes 113, as shown in FIG. 47.
Further, suicide layers 119 are formed on upper surfaces of the N-type semiconductor layers 105, the P-type semiconductor layers 118 and the gate electrodes 113 by sputtering or lamp annealing, and a barrier metal layer 120 and an aluminum interconnect line 121 are deposited on the overall surface (FIG. 48). FIG. 49 is a sectional view taken along the line Qxe2x80x94Q in FIG. 48. Referring to FIG. 49, isolation oxide films 122 and P-type semiconductor layers 123 are provided on both sides of each trench 200. The aluminum interconnect line 121 is connected with each gate electrode 113 on end portions of each trench 200 through the silicide layers 119 and the barrier metal layer 120.
The conventional trench MOS gates are formed in the aforementioned manner in the structure shown in FIGS. 48 and 49. Therefore, the gate oxide film 111 is locally reduced in thickness on openings C and bottom portions D of the trenches 200. Particularly in the openings C, convex corners appear in the gate oxide film 111 on the interfaces between the same and the gate electrodes 113. In the openings C, further, the gate oxide film 111 is damaged by etching of the gate electrode material layer 112 in the steps shown in FIGS. 43 and 44 to deteriorate the characteristics of the gate oxide film 111, as a first problem.
If the aluminum interconnect line 121 is inferior in flatness, the trench MOS gates are readily broken by an impact in an operation (on-cell bonding) of bonding aluminum thin wires of 50 to 400 xcexcm in diameter to the aluminum interconnect line 121 in an assembly step for transistors employing the trench MOS gates. Further, contact areas of the aluminum interconnect line 121 and the aluminum thin wires may tend to be reduced, to increase the resistance in the contact parts. In this case, the resistance of the transistors employing the trench MOS gates is apparently increased in ON states, as a second problem.
If the aluminum interconnect line 121 is formed in a large thickness in order to solve the second problem, a wafer provided with the trench MOS gates so remarkably warps that it is difficult to carry out an exposure step, as a third problem.
A semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate having a main surface, a trench having an opening on the main surface and a bottom portion in the semiconductor substrate respectively, an insulating film which is provided on an inner wall of the trench and a portion of the main surface around the opening, and a conductive material film which is provided oppositely to the semiconductor substrate through the insulating film and has a head portion which is farther from the opening of the trench than the main surface, and an end surface of the head portion is separated from the bottom portion of the trench than the inner wall by at least 0.2 xcexcm.
According to a second aspect of the present invention, the diameter of the head portion is at least 1.3 times the diameter of the inner wall of the trench in a linearly extending portion of the trench.
A method of fabricating a semiconductor device according to a third aspect of the present invention comprises steps of (a) preparing a semiconductor substrate having a main surface, b) forming a trench having an opening on the main surface and a bottom portion in the semiconductor substrate respectively, (c) forming an insulating film on an inner wall of the trench and a portion of the main surface around the opening, (d) forming a conductive material film covering the insulating film, and (e) selectively removing a part of the conductive material film which is separated from the opening than the inner wall of the trench by at least 0.2 xcexcm thereby forming a head portion.
According to a fourth aspect of the present invention, the diameter of the head portion is at least 1.3 times the diameter of the inner wall of the trench in a linearly extending portion of the trench.
In the semiconductor device and the method of fabricating a semiconductor device according to the first to fourth aspects of the present invention, a part of the insulating film close to the opening of the trench is not subjected to etching for shaping the conductive material film, so that the quality of the insulating film located on the opening is not deteriorated by plasma damage resulting from the etching. Thus, a trench MOS gate having excellent characteristics can be obtained.
A method of fabricating a semiconductor device according to a fifth aspect of the present invention comprises steps of (a) preparing a semiconductor substrate having a main surface, (b) forming a hole having an opening on the main surface and a bottom portion in the semiconductor substrate respectively, (c) annealing a structure obtained in the step (b), (d) forming a sacrifice oxide film by oxidizing an inner wall of the hole, (e) forming a trench by removing the sacrifice oxide film, (f) forming an insulating film by oxidizing an inner wall of the trench, and (g) forming a conductive material film covering the insulating film.
In the method of fabricating a semiconductor device according to the fifth aspect of the present invention, defects caused in the semiconductor substrate in formation of the hole concentrate to the inner wall of the hole by annealing to be removed by formation and removal of the sacrifice oxide film, whereby the insulating film obtained by oxidizing the trench excellently serves as a gate insulating film.
A semiconductor device according to a sixth aspect of the present invention comprises a gate electrode presenting a MOS structure, a first conductive layer provided on the gate electrode, and a second conductive layer, intervening between the gate electrode and the first conductive layer, having higher strength than the first conductive layer.
In the semiconductor device according to the sixth aspect of the present invention, the second conductive layer serves as a buffer for the gate electrode in bonding of the first conductive layer. Further, the flatness of the first conductive layer is improved due to the intervention of the second conductive layer. Therefore, the gate electrode presenting the MOS structure is prevented from being broken by an impact of bonding, or resistance of a transistor employing the same is prevented from being apparently increased in an ON state.
A method of fabricating a semiconductor device according to a seventh aspect of the present invention comprises steps of (a) forming a gate electrode presenting a MOS structure on a semiconductor substrate, b) forming a first conductive layer on the gate electrode, (c) patterning the first conductive layer, and (d) forming a second conductive layer on the first conductive layer.
In the method of fabricating a semiconductor device according to the seventh aspect of the present invention, the total thickness of the first and second conductive layers present above the gate electrode is increased. Further, the second conductive layer is formed after the area of the first conductive layer is reduced by patterning, whereby the semiconductor substrate is inhibited from warping. Therefore, it is possible to avoid such a situation that exposure cannot be performed while relaxing an impact of bonding against the second conductive layer.
According to an eighth aspect of the present invention, the step (c) includes a step of (c-1) patterning the first conductive layer while dividing the same into a first part which is connected to the gate electrode and the second conductive layer and a second part which is connected to an impurity region forming a MOS transistor with the gate electrode, and the method further comprises a step of (e) forming an interlayer insulating film intervening between the first part and the second conductive layer between the steps (c) and (d).
In the method of fabricating a semiconductor device according to the eighth aspect of the present invention, shorting between the second conductive layer and the gate electrode can be prevented while providing the second conductive layer on the first conductive layer.
An object of the present invention is to provide a semiconductor device which improves the characteristics of a gate oxide film and a method of fabricating the same.